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document no. e0671e20 (ver. 2.0) date published april 2005 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2005 data sheet 2gb registered ddr2 sdram dimm ebe21rd4aefa (256m words 72 bits, 2 ranks) description the ebe21rd4aefa is a 256m words 72 bits, 2 ranks ddr2 sdram module, mounting 36 pieces of 512m bits ddr2 sdram sealed in fbga ( bga ? ) package. read and write operations are performed at the cross points of the ck and the /ck. this high- speed data transfer is rea lized by the 4bits prefetch- pipelined architecture. data strobe (dqs and /dqs) both for read and write are available for high speed and reliable data bus design. by setting extended mode register, the on-chip delay locked loop (dll) can be set enable or disable. this module provides high density mounting without utilizing surface mount technology. decoupling capacitors are mounted beside each fbga ( bga) on the module board. note: do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. features ? 240-pin socket type dual in line memory module (dimm) ? pcb height: 30.0mm ? lead pitch: 1.0mm ? lead-free ? power supply: vdd, vddq = 1.8v 0.1v ? data rate: 533mbps /400mbps (max.) ? sstl_18 compatible i/o ? double-data-rate architecture: two data transfers per clock cycle ? bi-directional, data strobe (dqs and /dqs) is transmitted /received with data, to be used in capturing data at the receiver ? dqs is edge aligned with data for reads; center aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data referenced to both edges of dqs ? four internal banks for concurrent operation (components) ? burst length: 4, 8 ? /cas latency (cl): 3, 4, 5 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? average refresh period ? 7.8 s at 0 c tc + 85 c ? 3.9 s at + 85 c < tc + 95 c ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance ad justment and on-die- termination for better signal quality ? /dqs can be disabled for single-ended data strobe operation ? 1 piece of pll clock driver, 4 piece of register driver and 1 piece of serial eeprom (2k bits eeprom) for presence detect (pd)
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 2 ordering information part number data rate mbps (max.) component jedec speed bin* 1 (cl-trcd-trp) package contact pad mounted devices EBE21RD4AEFA-5C-E 533 ddr2-533 (4-4-4) ede5104aesk -5c-e ebe21rd4aefa-4a-e 400 ddr2-400 (3-3-3) 240-pin dimm (lead-free) gold ede5104aesk -5c-e ede5104aesk -4a-e notes: 1. module /cas latency = component cl + 1. pin configurations 1 pin front side back side 64 pin 65 pin 120 pin 121 pin 184 pin 185 pin 240 pin pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vref 61 a4 121 vss 181 vdd 2 vss 62 vdd 122 dq4 182 a3 3 dq0 63 a2 123 dq5 183 a1 4 dq1 64 vdd 124 vss 184 vdd 5 vss 65 vss 125 dqs9 185 ck0 6 /dqs0 66 vss 126 /dqs9 186 /ck0 7 dqs0 67 vdd 127 vss 187 vdd 8 vss 68 nc/par _ in 128 dq6 188 a0 9 dq2 69 vdd 129 dq7 189 vdd 10 dq3 70 a10 130 vss 190 ba1 11 vss 71 ba0 131 dq12 191 vdd 12 dq8 72 vdd 132 dq13 192 /ras 13 dq9 73 /we 133 vss 193 /cs0 14 vss 74 /cas 134 dqs10 194 vdd 15 /dqs1 75 vdd 135 /dqs10 195 odt0 16 dqs1 76 /cs1 136 vss 196 a13 17 vss 77 odt1 137 nc 197 vdd 18 /reset 78 vdd 138 nc 198 vss 19 nc 79 vss 139 vss 199 dq36 20 vss 80 dq32 140 dq14 200 dq37 21 dq10 81 dq33 141 dq15 201 vss 22 dq11 82 vss 142 vss 202 dqs13 23 vss 83 /dqs4 143 dq20 203 /dqs13 24 dq16 84 dqs4 144 dq21 204 vss 25 dq17 85 vss 145 vss 205 dq38 26 vss 86 dq34 146 dqs11 206 dq39 27 /dqs2 87 dq35 147 /dqs11 207 vss 28 dqs2 88 vss 148 vss 208 dq44
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 3 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 29 vss 89 dq40 149 dq22 209 dq45 30 dq18 90 dq41 150 dq23 210 vss 31 dq19 91 vss 151 vss 211 dqs14 32 vss 92 /dqs5 152 dq28 212 /dqs14 33 dq24 93 dqs5 153 dq29 213 vss 34 dq25 94 vss 154 vss 214 dq46 35 vss 95 dq42 155 dqs12 215 dq47 36 /dqs3 96 dq43 156 /dqs12 216 vss 37 dqs3 97 vss 157 vss 217 dq52 38 vss 98 dq48 158 dq30 218 dq53 39 dq26 99 dq49 159 dq31 219 vss 40 dq27 100 vss 160 vss 220 nc 41 vss 101 sa2 161 cb4 221 nc 42 cb0 102 nc 162 cb5 222 vss 43 cb1 103 vss 163 vss 223 dqs15 44 vss 104 /dqs6 164 dqs17 224 /dqs15 45 /dqs8 105 dqs6 165 /dqs17 225 vss 46 dqs8 106 vss 166 vss 226 dq54 47 vss 107 dq50 167 cb6 227 dq55 48 cb2 108 dq51 168 cb7 228 vss 49 cb3 109 vss 169 vss 229 dq60 50 vss 110 dq56 170 vdd 230 dq61 51 vdd 111 dq57 171 cke1 231 vss 52 cke0 112 vss 172 vdd 232 dqs16 53 vdd 113 /dqs7 173 nc 233 /dqs16 54 nc 114 dqs7 174 nc 234 vss 55 nc/err _ out 115 vss 175 vdd 235 dq62 56 vdd 116 dq58 176 a12 236 dq63 57 a11 117 dq59 177 a9 237 vss 58 a7 118 vss 178 vdd 238 vddspd 59 vdd 119 sda 179 a8 239 sa0 60 a5 120 scl 180 a6 240 sa1
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 4 pin description pin name function a0 to a13 address input row address a0 to a13 column address a0 to a9, a11 a10 (ap) auto precharge ba0, ba1 bank select address dq0 to dq63 data input/output cb0 to cb7 check bit (data input/output) /ras row address strobe command /cas column address strobe command /we write enable /cs0, /cs1 chip select cke0, cke1 clock enable ck0 clock input /ck0 differential clock input dqs0 to dqs17, /dqs0 to /dqs17 input and output data strobe scl clock input for serial pd sda data input/output for serial pd sa0 to sa2 serial address input vdd power for internal circuit vddspd power for serial eeprom vref input reference voltage vss ground odt0, odt1 odt control /reset reset pin (forces register and pll inputs low) * 1 par _ in* 2 parity bit for the address and control bus err _ out* 2 parity error found on the address and control bus nc no connection notes: 1. reset pin is connected to both oe of pll and reset to register. 2. nc/err _ out (pin 55) and nc/par _ in (pin 68) are for optional function to check address and command parity.
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 5 serial pd matrix* 1 byte no. function described bit7 bit6 bit5 bi t4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes utilized by module manufacturer 1 0 0 0 0 0 0 0 80h 128 bytes 1 total number of bytes in serial pd device 0 0 0 0 1 0 0 0 08h 256 bytes 2 memory type 0 0 0 0 1 0 0 0 08h ddr2 sdram 3 number of row address 0 0 0 0 1 1 1 0 0eh 14 4 number of column address 0 0 0 0 1 0 1 1 0bh 11 5 number of dimm ranks 0 1 1 0 0 0 0 1 61h 2 6 module data width 0 1 0 0 1 0 0 0 48h 72 7 module data width continuation 0 0 0 0 0 0 0 0 00h 0 8 voltage interface level of this assembly 0 0 0 0 0 1 0 1 05h sstl 1.8v 9 ddr sdram cycle time, cl = 5 -5c 0 0 1 1 1 1 0 1 3dh 3.75ns* 1 -4a 0 1 0 1 0 0 0 0 50h 5.0ns* 1 10 sdram access from clock (tac) -5c 0 1 0 1 0 0 0 0 50h 0.5ns* 1 -4a 0 1 1 0 0 0 0 0 60h 0.6ns* 1 11 dimm configuration type 0 0 0 0 0 0 1 0 02h ecc 12 refresh rate/type 1 0 0 0 0 0 1 0 82h 7.8 s 13 primary sdram width 0 0 0 0 0 1 0 0 04h 4 14 error checking sdram width 0 0 0 0 0 1 0 0 04h 4 15 reserved 0 0 0 0 0 0 0 0 00h 0 16 sdram device attributes: burst length supported 0 0 0 0 1 1 0 0 0ch 4,8 17 sdram device attributes: number of banks on sdram device 0 0 0 0 0 1 0 0 04h 4 18 sdram device attributes: /cas latency 0 0 1 1 1 0 0 0 38h 3, 4, 5 19 reserved 0 0 0 0 0 0 0 0 00h 0 20 dimm type information 0 0 0 0 0 0 0 1 01h registered 21 sdram module attributes 0 0 0 0 0 0 0 0 00h normal 22 sdram device attributes: general 0 0 0 0 0 0 0 1 01h weak driver 23 minimum clock cycle time at cl = 4 -5c 0 0 1 1 1 1 0 1 3dh 3.75ns* 1 -4a 0 1 0 1 0 0 0 0 50h 5.0ns* 1 24 maximum data access time (tac) from clock at cl = 4 -5c 0 1 0 1 0 0 0 0 50h 0.5ns* 1 -4a 0 1 1 0 0 0 0 0 60h 0.6ns* 1 25 minimum clock cycle time at cl = 3 0 1 0 1 0 0 0 0 50h 5.0ns* 1 26 maximum data access time (tac) from clock at cl = 3 0 1 1 0 0 0 0 0 60h 0.6ns* 1 27 minimum row precharge time (trp) 0 0 1 1 1 1 0 0 3ch 15ns 28 minimum row active to row active delay (trrd) 0 0 0 1 1 1 1 0 1eh 7.5ns 29 minimum /ras to /cas delay (trcd) 0 0 1 1 1 1 0 0 3ch 15ns
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 30 minimum active to precharge time (tras) -5c 0 0 1 0 1 1 0 1 2dh 45ns -4a 0 0 1 0 1 0 0 0 28h 40ns 31 module rank density 0 0 0 0 0 0 0 1 01h 1gb 32 address and command setup time before clock (tis) -5c 0 0 1 0 0 1 0 1 25h 0.25ns* 1 -4a 0 0 1 1 0 1 0 1 35h 0.35ns* 1 33 address and command hold time after clock (tih) -5c 0 0 1 1 1 0 0 0 38h 0.38ns* 1 -4a 0 1 0 0 1 0 0 0 48h 0.48ns* 1 34 data input setup time before clock (tds) -5c 0 0 0 1 0 0 0 0 10h 0.10ns* 1 -4a 0 0 0 1 0 1 0 1 15h 0.15ns* 1 35 data input hold time after clock (tdh) -5c 0 0 1 0 0 0 1 1 23h 0.23ns* 1 -4a 0 0 1 0 1 0 0 0 28h 0.28ns* 1 36 write recovery time (twr) 0 0 1 1 1 1 0 0 3ch 15ns* 1 37 internal write to read command delay (twtr) -5c 0 0 0 1 1 1 1 0 1eh 7.5ns* 1 -4a 0 0 1 0 1 0 0 0 28h 10ns* 1 38 internal read to precharge command delay (trtp) 0 0 0 1 1 1 1 0 1eh 7.5ns* 1 39 memory analysis probe characteristics 0 0 0 0 0 0 0 0 00h tbd 40 extension of byte 41 and 42 0 0 0 0 0 0 0 0 00h undefined 41 active command period (trc) -5c 0 0 1 1 1 1 0 0 3ch 60ns* 1 -4a 0 0 1 1 0 1 1 1 37h 55 ns* 1 42 auto refresh to active/ auto refresh command cycle (trfc) 0 1 1 0 1 0 0 1 69h 105ns* 1 43 sdram tck cycle max. (tck max.) 1 0 0 0 0 0 0 0 80h 8ns* 1 44 dout to dqs skew -5c 0 0 0 1 1 1 1 0 1eh 0.30ns* 1 -4a 0 0 1 0 0 0 1 1 23h 0.35ns* 1 45 data hold skew (tqhs) -5c 0 0 1 0 1 0 0 0 28h 0.40ns* 1 -4a 0 0 1 0 1 1 0 1 2dh 0.45ns* 1 46 pll relock time 0 0 0 0 1 1 1 1 0fh 15 s 47 to 61 0 0 0 0 0 0 0 0 00h 62 spd revision 0 0 0 1 0 0 0 0 10h rev. 1.0 63 checksum for bytes 0 to 62 -5c 0 1 0 0 1 1 0 1 4dh -4a 1 1 0 0 0 1 1 1 c7h 64 to 65 manufacturer?s jedec id code 0 1 1 1 1 1 1 1 7fh continuation code 66 manufacturer?s jedec id code 1 1 1 1 1 1 1 0 feh elpida memory
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 7 byte no. function described bit7 bit6 bit5 bi t4 bit3 bit2 bit1 bit0 hex value comments 67 to 71 manufacturer?s jedec id code 0 0 0 0 0 0 0 0 00h 72 manufacturing location (ascii-8bit code) 73 module part number 0 1 0 0 0 1 0 1 45h e 74 module part number 0 1 0 0 0 0 1 0 42h b 75 module part number 0 1 0 0 0 1 0 1 45h e 76 module part number 0 0 1 1 0 0 1 0 32h 2 77 module part number 0 0 1 1 0 0 0 1 31h 1 78 module part number 0 1 0 1 0 0 1 0 52h r 79 module part number 0 1 0 0 0 1 0 0 44h d 80 module part number 0 0 1 1 0 1 0 0 34h 4 81 module part number 0 1 0 0 0 0 0 1 41h a 82 module part number 0 1 0 0 0 1 0 1 45h e 83 module part number 0 1 0 0 0 1 1 0 46h f 84 module part number 0 1 0 0 0 0 0 1 41h a 85 module part number 0 0 1 0 1 1 0 1 2dh ? 86 module part number -5c 0 0 1 1 0 1 0 1 35h 5 -4a 0 0 1 1 0 1 0 0 34h 4 87 module part number -4a 0 1 0 0 0 0 0 1 41h a -5c 0 1 0 0 0 0 1 1 43h c 88 module part number 0 0 1 0 1 1 0 1 2dh ? 89 module part number 0 1 0 0 0 1 0 1 45h e 90 module part number 0 0 1 0 0 0 0 0 20h (space) 91 revision code 0 0 1 1 0 0 0 0 30h initial 92 revision code 0 0 1 0 0 0 0 0 20h (space) 93 manufacturing date year code (bcd) 94 manufacturing date week code (bcd) 95 to 98 module serial number 99 to 127 manufacture specific data notes: 1. these specificati ons are defined based on component specification, not module.
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 8 block diagram dm /cs dqs /dqs dq0 to dq3 4 dqs0 r s d0 /rcs0 vss dq8 to dq11 4 dqs1 r s r s r s r s r s r s r s r s /cs0 * 2 /cs1 * 2 ba0 to ba1 a0 to a13 /ras /cas cke0 cke1 /we /odt0 /odt1 /rcs0 -> /cs: sdrams d0 to d17 /rcs1 -> /cs: sdrams d18 to d35 rba0 to rba1 -> ba0 to ba1: sdrams d0 to d35 ra0 to ra13 -> a0 to a13: sdrams d0 to d35 /rras -> /ras: sdrams d0 to d35 /rcas -> /cas: sdrams d0 to d35 rcke0 -> cke: sdrams d0 to d17 rcke1 -> cke: sdrams d18 to d35 /rwe -> /we: sdrams d0 to d35 rodt0 -> odt: sdrams d0 to d17 rodt1 -> odt: sdrams d18 to d35 r e g i s t e r /pck7 * 3 /reset* 3 /dqs0 d1 /dqs1 dq16 to dq19 4 dqs2 r s d2 /dqs2 dq24 to dq27 4 dqs3 r s d3 /dqs3 dq32 to dq35 4 dqs4 r s d4 /dqs4 dq40 to dq43 4 dqs5 r s d5 /dqs5 dq48 to dq51 4 dqs6 r s d6 /dqs6 dq56 to dq59 4 dqs7 r s d7 /dqs7 cb0 to cb3 4 dqs8 r s dq0 to dq3 d8 /dqs8 d18 d19 d20 d21 d22 d23 d24 d25 d26 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 r s /rst pck7 * 3 notes: 1. dq wring may be changed within a nibble. 2. /cs0 connects to d/cs and /cs1 connects to /csr on register1 and register2. /cs1 connects to d/cs and /cs0 connects to /csr on register3 and register4. 3. /reset, pck7 and /pck7 connect to all registers. cke and /odt connect to a register. other signals connect to two of four registers. p l l oe ck0 /ck0 /reset pck0 to pck6, pck8, pck9 -> ck: sdrams d0 to d35 /pck0 to /pck6, /pck8, /pck9 -> /ck: sdrams d0 to d35 pck7 -> ck: register /pck7 -> /ck: register d0 to d35: 512m bits ddr2 sdram u0: 2k bits eeprom r s : 22 ? pll: cua877 register: sstua32866 serial pd sda a0 a1 a2 sa0 sa1 sa2 scl scl u0 sda wp serial pd d0 to d35 d0 to d35 d0 to d35 vddspd vss vref vdd r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s /rcs1 d9 d10 d11 d12 d13 d14 d15 d16 dq0 to dq3 d17 d27 d28 d29 d30 d31 d32 d33 d34 d35 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq4 to /dq7 4 dqs9 r s dq12 to dq15 4 r s /dqs9 dq20 to dq23 4 r s dq28 to dq31 4 r s dq36 to dq39 4 r s dq44 to dq47 4 r s dq52 to dq55 4 r s dq60 to dq63 4 r s cb4 to cb7 4 r s dqs10 /dqs10 dqs11 /dqs11 dqs12 /dqs12 dqs13 /dqs13 dqs14 /dqs14 dqs15 /dqs15 dqs16 /dqs16 dqs17 /dqs17 r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs r s r s r s
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 9 differential clock net wiring (ck0, /ck0) 120 ? 0ns (nominal) 120 ? 120 ? ck0 notes: 1. the clock delay from the input of the pll clock to the input of any sdram or register willl be set to 0ns (nominal). 2. input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. only one pll output is shown per output type. any additional pll outputs will be wired in a similar manner. 4. termination resistors for the pll feedback path clocks are located as close to the input pin of the pll as possible. c /ck0 sdram stack pll feedback in in out1 out'n' feedback out sdram stack 120 ? register 1 register 2 register 4 120 ? c register 3 c
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 10 electrical specifications ? all voltages are referenced to vss (gnd). absolute maximum ratings parameter symbol value unit note voltage on any pin relative to vss vt ?0.5 to +2.3 v 1 supply voltage relative to vss vdd ?0.5 to +2.3 v short circuit output current ios 50 ma 1 power dissipation pd 18 w operating case temperature tc 0 to +95 c 1, 2 storage temperature tstg ?55 to +100 c 1 notes: 1 ddr2 sdram component specification. 2. supporting 0 c to +85c and being able to extend to +95c with doubling auto-refresh commands in frequency to a 32ms period (trefi = 3.9 s) and higher temperature self-refresh entry via the control of emrs (2) bit a7 is required. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating conditions (tc = 0c to +85 c) (ddr2 sdram component specification) parameter symbol min. typ. max. unit notes supply voltage vdd, vddq 1.7 1.8 1.9 v 4 vss 0 0 0 v vddspd 1.7 ? 3.6 v input reference voltage vref 0.49 vddq 0.50 vddq 0.51 vddq v 1, 2 termination voltage vtt vref ? 0.04 vref vref + 0.04 v 3 dc input logic high vih (dc) vref + 0.125 ? vddq + 0.3v v dc input low vil (dc) ? 0.3 ? vref ? 0.125 v ac input logic high vih (ac) vref + 0.250 ? ? v ac input low vil (ac) ? ? vref ? 0.250 v notes: 1. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 vddq of the transmitting device and vref are expected to track variations in vddq. 2. peak to peak ac noise on vref may not exceed 2% vref (dc). 3. vtt of transmitting device must track vref of receiving device. 4. vddq must be equal to vdd.
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 11 dc characteristics 1 (tc = 0c to +85 c, vdd = 1.8v 0.1v, vss = 0v) parameter symbol grade max unit test condition -5c 3660 operating current (act-pre) idd0 -4a 3250 ma one bank; tck = tck (idd), trc = trc (idd), tras = tras min.(idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data bus inputs are switching -5c 3980 operating current (act-read-pre) idd1 -4a 3560 ma one bank; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), trc = trc (idd), tras = tras min.(idd); trcd = trcd (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data pattern is same as idd4w -5c 930 precharge power-down standby current idd2p -4a 810 ma all banks idle; tck = tck (idd); cke is l; other control and address bus inputs are stable; data bus inputs are floating -5c 1470 precharge quiet standby current idd2q -4a 1250 ma all banks idle; tck = tck (idd); cke is h, /cs is h; other control and address bus inputs are stable; data bus inputs are floating -5c 1650 idle standby current idd2n -4a 1430 ma all banks idle; tck = tck (idd); cke is h, /cs is h; other control and address bus inputs are switching; data bus inputs are switching -5c 2010 idd3p-f -4a 1790 ma fast pdn exit mrs(12) = 0 -5c 1470 active power-down standby current idd3p-s -4a 1250 ma all banks open; tck = tck (idd); cke is l; other control and address bus inputs are stable; data bus inputs are floating slow pdn exit mrs(12) = 1 -5c 2940 active standby current idd3n -4a 2710 ma all banks open; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; other control and address bus inputs are switching; data bus inputs are switching -5c 4830 operating current (burst read operating) idd4r -4a 4140 ma all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data pattern is same as idd4w -5c 4830 operating current (burst write operating) idd4w -4a 4140 ma all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data bus inputs are switching
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 12 parameter symbol grade max unit test condition -5c 6200 auto-refresh current idd5 -4a 5710 ma tck = tck (idd); refresh command at every trfc (idd) interval; cke is h, /cs is h between valid commands; other control and address bus inputs are switching; data bus inputs are switching self-refresh current idd6 310 ma self refresh mode; ck and /ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating -5c 7420 operating current (bank interleaving) idd7 -4a 6850 ma all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = trcd (idd) ? 1 tck (idd); tck = tck (idd), trc = trc (idd), trrd = trrd(idd), trcd = 1 tck (idd); cke is h, cs is h between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4w; notes: 1. idd specifications are tested after the device is properly initialized. 2. input slew rate is specifi ed by ac input test condition. 3. idd parameters are spec ified with odt disabled. 4. data bus consists of dq, dm, dqs, /dqs, rdqs, /rdqs, ldqs , /ldqs, udqs, and /udqs. idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd l is defined as vin vil (ac) (max.) h is defined as vin vih (ac) (min.) stable is defined as inputs stable at an h or l level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between h and l every other clock cycle (once per two clocks) for address and control signals, and inputs changing between h and l every ot her data transfer (once per clock) for dq signals not including masks or strobes. 6. refer to ac timing for idd test conditions. ac timing for idd test conditions for purposes of idd testing, the fo llowing parameters are to be utilized. ddr2-533 ddr2-400 parameter 4-4-4 3-3-3 unit cl(idd) 4 3 tck trcd(idd) 15 15 ns trc(idd) 60 55 ns trrd(idd) 7.5 7.5 ns tck(idd) 3.75 5 ns tras(min.)(idd) 45 40 ns tras(max.)(idd) 70000 70000 ns trp(idd) 15 15 ns trfc(idd) 105 105 ns
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 13 dc characteristics 2 (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter symbol value unit notes input leakage current ? ili ? 2 a vdd vin vss output leakage current ? ilo ? 5 a vddq vout vss minimum required output pull-up under ac test load voh vtt + 0.603 v 5 maximum required output pull-down under ac test load vol vtt ? 0.603 v 5 output timing measurement reference level votr 0.5 vddq v 1 output minimum sink dc current iol +13.4 ma 3, 4, 5 output minimum source dc current ioh ? 13.4 ma 2, 4, 5 notes: 1. the vddq of the dev ice under test is referenced. 2. vddq = 1.7v; vout = 1.42v. 3. vddq = 1.7v; vout = 0.28v. 4. the dc value of vref applied to the receiving device is expected to be set to vtt. 5. after ocd calibration to 18 ? at tc = 25 c, vdd = vddq = 1.8v. dc characteristics 3 (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter symbol min. max. unit note ac differential input voltage vid (ac) 0.5 vddq + 0.6 v 1, 2 ac differential cross point voltage vix (ac) 0.5 vddq ? 0.175 0.5 vddq + 0.175 v 2 ac differential cross point voltage vox (ac) 0.5 vddq ? 0.125 0.5 vddq + 0.125 v 3 notes: 1. vid(ac) specifies the input differential voltage |vtr -vcp| required for switching, where vtr is the true input signal (such as ck, dqs, ldqs or udqs) and vcp is the complementary input signal (such as /ck, /dqs, /ldqs or /udqs). the minimum value is equal to vih(ac) ? vil(ac). 2. the typical value of vix(ac ) is expected to be about 0.5 vddq of the transmitting device and vix(ac) is expected to track variations in vddq . vix(ac) in dicates the voltage at which differential input signals must cross. 3. the typical value of vox(ac) is expected to be about 0.5 vddq of the transmitting device and vox(ac) is expected to track variations in vddq . vox(ac) indicates the voltage at which differential output signals must cross. crossing point vssq vtr vcp vid vix or vox vddq differential signal levels*1, 2
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 14 odt dc electrical characteristics (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter symbol min typ max unit notes rtt effective impedance value for emrs (a6, a2) = 0, 1 ; 75 ? rtt1(eff) 60 75 90 ? 1 rtt effective impedance value for emrs (a6, a2) = 1, 0 ; 150 ? rtt2(eff) 120 150 180 ? 1 rtt effective impedance value for emrs (a6, a2) = 1, 1 ; 50 ? rtt3(eff) 40 50 60 ? 1 deviation of vm with respect to vddq/2 ? vm ? 6 ? + 6 % 1 note: 1. test condition for rtt measurements. measurement definition for rtt(eff) apply vih (ac) and vil (ac) to test pin separately, th en measure current i(vih(ac)) and i(vil(ac)) respectively. vih(ac), and vddq values defined in sstl _ 18. vih(ac) ? vil(ac) i(vih(ac)) ? i(vil(ac)) rtt(eff) = measurement definition for ? vm measure voltage (vm) at test pin (midpoint) with no load. 2 vm vddq ? vm = 100% ? 1 ocd default characteristics (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter min typ max unit notes output impedance 12.6 18 23.4 ? 1 pull-up and pull-down mismatch 0 ? 4 ? 1, 2 output slew rate 1.5 ? 5 v/ns 3, 4 notes: 1. impedance measurement condition for out put source dc current: vddq = 1.7v; vout = 1420mv; (vout ? vddq)/ioh must be less than 23.4 ? for values of vout between vddq and vddq ? 280mv. impedance measurement condition for output si nk dc current: vddq = 1.7v; vout = 280mv; vout/iol must be less than 23.4 ? for values of vout between 0v and 280mv. 2. mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. slew rate measured from vil(ac) to vih(ac). 4. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. pin capacitance (ta = 25c, vdd = 1.8v 0.1v) parameter symbol pins min. max. unit notes input capacitance ci1 address, /ras, /cas, /we, /cs, cke, odt 2.5 3.5 pf 1 input capacitance ci2 ck, /ck 2 3 pf 2 data and dqs input/output capacitance co dq, dqs, /dqs, cb 2.5 4 pf 3 notes: 1. register component specification. 2. pll component specification. 3. ddr2 sdram component specification.
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 15 ac characteristics (tc = 0c to +85 c , vdd, vddq = 1.8v 0.1v, vss = 0v) (ddr2 sdram component specification) -5c -4a frequency (mbps) 533 400 parameter symbol min. max. min. max. unit notes /cas latency cl 4 5 3 5 tck active to read or write command delay trcd 15 ? 15 ? ns precharge command period trp 15 ? 15 ? ns active to active/auto refresh command time trc 60 ? 55 ? ns dq output access time from ck, /ck tac ? 500 +500 ? 600 +600 ps dqs output access time from ck, /ck tdqsck ? 450 +450 ? 500 +500 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min. (tcl, tch) ? min. (tcl, tch) ? ps clock cycle time tck 3750 8000 5000 8000 ps dq and dm input hold time tdh 225 ? 275 ? ps 5 dq and dm input setup time tds 100 ? 150 ? ps 4 control and address input pulse width for each input tipw 0.6 ? 0.6 ? tck dq and dm input pulse width for each input tdipw 0.35 ? 0.35 ? tck data-out high-impedance time from ck,/ck thz ? tac max. ? tac max. ps data-out low-impedance time from ck,/ck tlz ta c min. tac max. tac min. tac max. ps dqs-dq skew for dqs and associated dq signals tdqsq ? 300 ? 350 ps dq hold skew factor tqhs ? 400 ? 450 ps dq/dqs output hold time from dqs tqh thp ? tqhs ? thp ? tqhs ? ps write command to first dqs latching transition tdqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 ? 0.35 ? tck dqs input low pulse width tdqsl 0.35 ? 0.35 ? tck dqs falling edge to ck setup time tdss 0.2 ? 0.2 ? tck dqs falling edge hold time from ck tdsh 0.2 ? 0.2 ? tck mode register set command cycle time tmrd 2 ? 2 ? tck write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 ? 0.35 ? tck address and control input hold time tih 375 ? 475 ? ps 5 address and control input setup time tis 250 ? 350 ? ps 4 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to precharge command tras 45 70000 40 70000 ns active to auto-precharge delay trap trcd min. ? trcd min. ? ns active bank a to active bank b command period trrd 7.5 ? 7.5 ? ns write recovery time twr 15 ? 15 ? ns auto precharge write recovery + precharge time tdal (twr/tck)+ (trp/tck) ? (twr/tck)+ (trp/tck) ? tck 1
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 16 -5c -4a frequency (mbps) 533 400 parameter symbol min. max. min. max. unit notes internal write to read command delay twtr 7.5 ? 10 ? ns internal read to precharge command delay trtp 7.5 ? 7.5 ? ns exit self refresh to a non-read command txsnr trfc + 10 ? trfc + 10 ? ns exit self refresh to a read command txsrd 200 ? 200 ? tck exit precharge power down to any non-read command txp 2 ? 2 ? tck exit active power down to read command txard 2 ? 2 ? tck 3 exit active power down to read command (slow exit/low power mode) txards 6 ? al ? 6 ? al ? tck 2, 3 cke minimum pulse width (high and low pulse width) tcke 3 ? 3 ? tck output impedance test driver delay toit 0 12 0 12 ns auto refresh to active/auto refresh command time trfc 105 ? 105 ? ns average periodic refresh interval (0 c tc +85 c) trefi ? 7.8 ? 7.8 s (+85 c < tc +95 c) trefi ? 3.9 ? 3.9 s minimum time clocks remains on after cke asynchronously drops low tdelay tis + tck + tih ? tis + tck + tih ? ns notes: 1. for each of the terms above, if not alread y an integer, round to the next higher integer. 2. al: additive latency. 3. mrs a12 bit defines which active power down exit timing to be applied. 4. the figures of input waveform timing 1 and 2 are referenced from the input signal crossing at the vih(ac) level for a rising signal and vil(ac) for a falling signal applied to the device under test. 5. the figures of input waveform timing 1 and 2 are referenced from the input signal crossing at the vih(dc) level for a rising signal and vil(dc) for a falling signal applied to the device under test. dqs /dqs tds tdh tds tdh vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref ck /ck tis tih tis tih vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref input waveform timing 1 (tds, tdh) input waveform timing 2 (tis, tih)
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 17 odt ac electrical characteristics (d dr2 sdram component specification) parameter symbol min max unit notes odt turn-on delay taond 2 2 tck odt turn-on taon tac(min) tac(max) + 1000 ps 1 odt turn-on (power down mode) taonpd tac(min) + 2000 2tck + tac(max) + 1000 ps odt turn-off delay taofd 2.5 2.5 tck odt turn-off taof tac(min) tac(max) + 600 ps 2 odt turn-off (power down mode) taofpd tac(min) + 2000 2.5tck + tac(max) + 1000 ps odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck notes: 1. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistanc e is fully on. both are measured from taond. 2. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. ac input test conditions parameter symbol value unit notes input reference voltage vref 0.5 vddq v 1 input signal maximum peak to peak swing vswing(max.) 1.0 v 1 input signal maximum slew rate slew 1.0 v/ns 2, 3 notes: 1. input waveform timing is referenced to the inpu t signal crossing through the vref level applied to the device under test. 2. the input signal minimum slew rate is to be ma intained over the range from vil(dc) (max.) to vih(ac) (min.) for rising edges and the range from vih(dc) (min .) to vil(ac) (max.) for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil( ac) on the negative transitions. vswing(max.) ? tr ? tf start of falling edge input timing start of rising edge input timing vih (dc) (min.) ? vil (ac) (max.) ? tf falling slew = vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref vih (ac) min. ? vil (dc) (max.) ? tr rising slew = ac input test signal wave forms vtt measurement point dq rt =25 ? output load
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 18 pin functions ck, /ck (input pin) the ck and the /ck are the master clock inputs. all in puts except dms, dqss and dqs are referred to the cross point of the ck rising edge and the vref level. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dqs are referred to the cross point of the dqs and the vref level. dqss for write operation are referred to the cross point of the ck and the /ck. /cs (input pin) when /cs is low, commands and data can be input. when /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) these pins define operating commands (re ad, write, etc.) depending on the comb inations of their voltage levels. see "command operation". a0 to a13 (input pins) row address (ax0 to ax13) is determined by the a0 to the a13 level at the cross point of the ck rising edge and the vref level in a bank active command cycle. column addr ess (ay0 to ay9, ay11) is loaded via the a0 to the a9 and a11 at the cross point of the ck rising edge and the vref level in a read or a write command cycle. this column address becomes the starti ng address of a burst operation. a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1, ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. ba0, ba1 (input pin) ba0, ba1 are bank select signals (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. cke (input pin) cke controls power down and self-refresh. the powe r down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. the cke level must be kept for 1 ck cycle at least, that is , if cke changes at the cross point of the ck rising edge and the vref level with proper setup time tis, at the next ck rising edge cke level must be kept with proper hold time tih. dq, cb (input and output pins) data are input to and output from these pins. dqs (input and output pin) dqs and /dqs provide the read data strobes (as output) and the write data strobes (as input).
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 19 vdd (power supply pins) 1.8v is applied. (vdd is for the internal circuit.) vddspd (power supply pin) 1.8v is applied (f or serial eeprom). vss (power supply pin) ground is connected. /reset (input pin) lvcmos reset input. when /reset is low, all registers are reset. par _ in (parity input pin) parity bit for the address and control bus. err _ out (error output pin) parity error found on the address and control bus. detailed operation part and timing waveforms refer to the ede5104aesk, ede5108aes k datasheet (e0562e). dm pins of component device fixed to vss level on the module board. dimm /cas latency = component cl + 1 for registered type.
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 20 physical outline detail a 0.20 0.15 2.50 0.20 1.00 133.35 (datum -a-) 63.00 55.00 a b 1 120 240 121 full r 0.80 0.05 unit: mm 1.27 0.10 3.00 4.00 min 10.00 4.00 17.80 30.00 4.00 max 0.5 min component area (front) component area (back) 5.00 detail b 3.80 1.50 0.10 2.50 4.00 full r (datum -a-) eca-ts2-0093-01
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 21 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
ebe21rd4aefa data sheet e0671e20 (ver. 2.0) 22 bga is a registered trademark of tessera, inc. all other trademarks are the intellectual property of their respective owners. m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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